1. Field of the Invention
The present invention relates to a semiconductor device having, on a single semiconductor substrate, a high-density region containing transistor elements arrayed at a high density and a low-density region containing transistor elements arrayed at a low density, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
There have heretofore been used semiconductor devices of various structures. For example, semiconductor memories such as DRAMs (Dynamic Random Access Memories) usually have a cell array region as a high-density region and a peripheral circuit region as a low-density region, disposed on a single semiconductor substrate.
The cell array region comprises a two-dimensional high-density array of identical transistor elements that form memory cells, and the peripheral circuit region comprises a low-density array of transistor elements that form various circuits including an XY decoder. In manufacturing such a semiconductor device, the transistor elements in the high-density region and the transistor elements in the low-density region are simultaneously fabricated.
The above conventional semiconductor device and a process of manufacturing the conventional semiconductor device will be described by way of example below with reference to FIGS. 1 through 7 of the accompanying drawings.
As shown in FIG. 1, DRAM 100 has cell array region 102 as a high-density region and peripheral circuit region 103 as a low-density region, disposed on single semiconductor substrate 101.
Cell array region 102 comprises a high-density array of identical transistor elements 111 that form memory cells 110, and peripheral circuit region 103 comprises a low-density array of transistor elements 112 that form various circuits including an XY decoder.
Transistor elements 111, 112 have respective source regions 111b, 112b and respective drain regions 111c, 112c formed by introducing an impurity into semiconductor substrate 101 by way of ion implantation. The gaps between source regions 111b, 112b and drain regions 111c, 112c function as respective gate regions 111a, 112a. In cell array region 102, a pair of adjacent transistor elements 111 sharing source region 111b make up memory cell 110. A plurality of memory cells are arranged in a substantially zigzag pattern (see FIG. 2). In peripheral circuit region 103, transistor elements 112 are arranged as desired to form peripheral circuits, though not shown. As a whole, transistor elements 112 in peripheral circuit region 103 are arranged at a density lower than transistor elements 111 in cell array region 102.
As described above, a plurality of memory cells 110 are arranged in a substantially zigzag pattern as schematically shown in FIG. 2. The structure of memory cell 110 will briefly be described below. In FIG. 2, transistor elements 111 and capacitors 113 in only one of a number of memory cells 110 are denoted by reference numerals.
Gate oxide films 115 are formed on gate regions 111a of transistor elements 111 of semiconductor substrate 101 shown in FIG. 1, and a plurality of striped gate electrodes 116, which extend vertically in FIG. 2, are disposed at given spaced intervals on the surfaces of gate oxide films 115. Gate electrodes 116 each comprise two layers including a polysilicon layer 117 and a tungsten silicide layer 118. Oxide films 119 are formed on the surfaces of gate electrodes 116. Side walls 120 comprising nitride films are formed on sides of oxide films 119 and gate electrodes 116.
Central contact electrode 121 is disposed in the gap between side walls 120 over source region 111b of transistor element 111. Outer contact electrodes 122 are disposed in the gaps between side walls 120 over drain regions 111c of transistor elements 111. Therefore, a pair of outer contact electrodes 122 are disposed on both sides of central contact electrode 121 in spaced-apart relation to each other. Outer contact electrodes 122 serve as drain electrodes of transistor elements 111, and central contact electrode 121 serves as a source electrode of transistor element 111. One central contact electrode 121 serves as a common source electrode of a pair of transistor elements 111.
Capacitors 113 are disposed upwardly of central contact electrode 121 and outer contact electrodes 122 and extend outwardly from positions above outer contact electrodes 122, i.e., remotely from a position above central contact electrode 121. Essentially, capacitor 113 is of a structure comprising a dielectric sandwiched between a pair of conductors (electrode plates or the like). Specifically, dielectric 113b is interposed between conductor 113a and conductive bit line 123. Spherical bodies 113c serve to increase the surface area of conductor 113a. 
With the above construction, as seen in plan in FIG. 2, a pair of transistor elements 111 are disposed on both sides of source region 111b below central contact electrode 121 in sharing relation to source region 111b. Capacitors 113 are disposed above positions outside of respective transistor elements 111. As shown at an enlarged scale in FIG. 3, a pair of transistor elements 111 and a pair of capacitors 113 make up a group that serves as a memory cell.
As shown in FIG. 2, a plurality of memory cells 110 are arranged in a zigzag pattern, forming a cell array region as a high-density region. Semiconductor substrate 101 has recesses in positions other than transistor elements 111, and STIs (Shallow Trench Isolations) 114 are disposed in the respective recesses to isolate memory cells 110 from each other. In appropriate positions between memory cells 110, the electrodes are rendered nonconductive by oxide insulating films 132 shown in FIG. 1, thus arranging independent memory cells 110 in the zigzag pattern.
A plurality of striped bit lines 123, which extend horizontally in FIG. 2, are disposed at given spaced intervals above gate electrodes 116 out of direct contact therewith. As shown in FIG. 1, bit line 123 has downward extensions 123a extending partially downwardly above central contact electrode 121 that is held in contact with downward extension 123a. Outer contact electrodes 122 are connected to capacitors 113 disposed thereabove.
In peripheral circuit region 103, transistor elements 112 comprising gate regions 112a, source regions 112b, and drain regions 112c are formed on semiconductor substrate 101, substantially as is the case with transistor elements 111 described above. Gate oxide films 115, gate electrodes 116 which consists of polysilicon layers 117 and tungsten silicide layers 118, and oxide layers 119 are successively disposed on gate regions 112a on the surface of semiconductor substrate 101. Side walls 120 consisting of nitride films are formed on sides of oxide films 119 and gate electrodes 116. Downward extensions 123a of bit lines 123 are disposed outside of side walls 120 and directly connected to drain regions 112c of semiconductor substrate 101, not via contact electrodes, and function as drain electrodes. Source electrodes (not shown) are connected to source regions 112b of semiconductor substrate 101. In this manner, a path is established for an output signal from a source electrode (not shown) of peripheral circuit region 103 to pass through source region 112b, gate region 112a, and drain region 112c of transistor element 112, then through bit line 123 and central contact electrode 121 into source region 111b of transistor element 111, and then pass through gate region 111a and drain region 111c thereof to outer contact electrodes 122.
A process of manufacturing the semiconductor device, i.e., DRAM 100 described above, will briefly be described below.
STIs 114 are formed in a given pattern in semiconductor substrate 101. Then, gate oxide film 115 having a thickness of 8.0 nm is formed on the surface of semiconductor substrate 101 in an area free of STIs 114.
Then, polysilicon layer 117 having a thickness of 100 nm, tungsten silicide layer 118 having a thickness of 150 nm, and oxide film 119 having a thickness of 150 nm are successively formed on the surface of semiconductor substrate 101, and thereafter etched in a given pattern to form two-layer gate electrodes 116 over gate regions 111a, 112a of transistor elements 111, 112.
First nitride film 131 having a thickness of 50 nm is formed uniformly on the surface of semiconductor substrate 101 with gate electrodes 116 thus formed thereon. Subsequently, cell array region 102 is masked, and first nitride film 131 in peripheral circuit region 103 is partly etched so as to remain only on sides of gate electrodes 116 in peripheral circuit region 103, thus forming side walls 120 and exposing gate oxide film 115 except for portions of gate electrodes 116.
After the mask is removed, an impurity is introduced by way of ion implantation, for example, to form source regions 111b, 112b and drain regions 111c, 112c, with the gaps between source regions 111b, 112b and drain regions 111c, 112c serving as gate regions 111a, 112a, thus forming transistor elements 111, 112 in semiconductor substrate 101.
Then, oxide insulating film 132 having a thickness of 20 nm is uniformly formed on the surfaces of cell array region 102 and peripheral circuit region 103. As shown in FIG. 4, interlayer insulating film 133 made of BPSG (Borophosphosilicate Glass) with an impurity included and having a thickness of 1.0 xcexcm is formed on the surface of oxide insulating film 132. In cell array region 102, since gate electrodes 116 are arranged at a high density, voids 134 may possibly be formed in interlayer insulating film 133. For this reason, interlayer insulating film 133 is annealed to reflow in an N2 atmosphere, for example, to eliminate produced voids 134.
Then, cell array region 102 is self-aligned using first nitride film 131 positioned on the sides of gate electrodes 116 as an etching stopper, thereby forming contact holes in interlayer insulating film 133 which reach semiconductor substrate 101. Contact electrodes 121, 122 are then formed in the contact holes. Finally, the assembly is annealed in a forming gas as of hydrogen to recover an interfacial level.
According to the above semiconductor device fabrication process, it is possible to simultaneously form transistor elements 111 arranged at a high density in cell array region 102 and transistor elements 112 arranged at a low density in peripheral circuit region 103.
Since cell array region 102 is self-aligned using first nitride film 131 as an etching stopper to form contact holes in interlayer insulating film 133, contact electrodes 121, 122 can reliably be formed in the gaps between transistor elements 111 that are arranged at a high density.
If thick first nitride film 131 that can be used as an etching stopper remains in the gaps between transistor elements 112 in peripheral circuit region 103, for example, and has a large area, then the assembly suffers excessive stresses when it is heated such as for annealing, tending to break the crystalline structure of semiconductor substrate 101. Because such thick first nitride film 131 blocks the forming gas used in the final annealing step, if it remains in the gaps between transistor elements 112 in peripheral circuit region 103, then an interfacial level fails to be recovered.
In the conventional semiconductor device fabrication process, peripheral circuit region 103 where transistor elements 112 are arranged at a low density does not suffer the above various drawbacks because thick first nitride film 131 is removed in the fabrication process.
In cell array region 102, since gate electrodes 116 are arranged at a high density, voids 134 may possibly occur in interlayer insulating film 133. In order to eliminate such voids 134, interlayer insulating film 133 may be annealed to conduct reflowing. As a higher density is sought, the aspect ratio of interlayer insulating film 133 positioned in the gaps between gate electrodes 116 becomes larger. For example, as shown in FIG. 5, if interlayer insulating film 133 positioned in the gaps between gate electrodes 116 has a width of 50 nm and a depth of 400 nm, then the aspect ratio thereof is 8. If the aspect ratio is 4 or higher, then sufficient reflowing cannot be achieved in interlayer insulating film 133 even if it is annealed according to an ordinary process, and voids 134 are liable to remain as shown in FIG. 6. If the annealing temperature is made higher or the annealing time is made longer to eliminate voids 134 in cell array region 102, then an impurity as of phosphorus or boron is diffused from interlayer insulating film 133 into semiconductor substrate 101 in peripheral circuit region 103, making it impossible to control the characteristics of transistor elements 112.
If the thickness of oxide insulating film 132 is increased to make it possible to reliably control the characteristics of transistor elements 112, the aspect ratio of interlayer insulating film 133 positioned in the gaps between gate electrodes 116 is further increased, making it more difficult to eliminate voids 134.
If attempts are made to allow easy reflowing of interlayer insulating film 133 for reliably eliminating voids 134, the density of the impurity in interlayer insulating film 133 is increased, resulting in an increase in the amount of the impurity diffused from interlayer insulating film 133 into semiconductor substrate 101 in peripheral circuit region 103. For example, if interlayer insulating film 133 is annealed in an atmosphere containing water vapor (water-vapor annealing), then reflowing of interlayer insulating film 133 is conducted well without changing the annealing time and temperature. However, as shown in FIG. 7, the amount of the impurity diffused from interlayer insulating film 133 into semiconductor substrate 101 in peripheral circuit region 103 is increased. This appears to be due to the fact that the barrier capability of oxide insulating film 132 is impaired by the water-vapor annealing. It has been confirmed that silicon of semiconductor substrate 101 is oxidized in the water-vapor annealing.
It is therefore an object of the present invention to provide a semiconductor device which has an array of transistor elements arranged at a high density, contact electrodes formed by self-alignment, and an interlayer insulating film free of voids, and a method of manufacturing such a semiconductor device.
To achieve the above object, there is provided a method of manufacturing a semiconductor device having, on a single semiconductor substrate, a high-density region containing transistor elements arrayed at a high density and a low-density region containing transistor elements arrayed at a low density. The method comprises the following steps. Firstly, a gate oxide film is formed on a surface of the semiconductor substrate. Gate electrodes are formed on a surface of the gate oxide film. Oxide films are formed on the gate electrodes. A first nitride film having a predetermined thickness is uniformly formed on the surface with the gate electrodes formed thereon. The high-density region of the semiconductor substrate is masked, and the first nitride film in only the low-density region is etched to expose the gate oxide film in gaps between gate electrodes. A second nitride film having a predetermined thickness is uniformly formed on the surface on which the first nitride film is etched. An interlayer insulating film with an impurity introduced therein is formed on a surface of the second nitride film. An assembly formed so far is annealed in an atmosphere containing water vapor. The high-density region is self-aligned using the first nitride film positioned on sides of the gate electrodes as an etching stopper to form contact holes reaching the semiconductor substrate in the interlayer insulating film. Contact electrodes connected to the semiconductor substrate are formed in the contact holes. An assembly formed so far is annealed with a forming gas to recover an interfacial level.
In the above method, voids in the interlayer insulating film are eliminated when the assembly is annealed in water vapor. Since the gate oxide film and the second nitride film are positioned on the surface of the semiconductor substrate in the low-density region, the second nitride film prevents an impurity from being diffused from the interlayer insulating film into the semiconductor substrate and also prevents the semiconductor substrate from being oxidized. Generally, a nitride film produces stresses when heated, e.g., when annealed, and cannot be formed in a large area in the low-density region. However, if the second nitride film is formed to an appropriate thickness, it does not produce stresses that would impair the semiconductor substrate in the low-density region. Generally, a nitride film tends to prevent a forming gas used when the assembly is finally annealed from being diffused into the semiconductor substrate. However, the second nitride film that is formed to an appropriate thickness does not prevent the forming gas from being diffused into the semiconductor substrate.
If nitride protective films, rather than the oxide films, are formed on the gate electrodes, then when the first nitride film in the low-density region is etched, the gate oxide film may be exposed in the gaps between gate electrodes, and the nitride protective films may be exposed on the gate electrodes. When the first nitride film in the low-density region is removed, the first nitride film in the high-density region is also etched. However, since the nitride protective films are formed on the gate electrodes, the gate electrodes are not exposed when the first nitride film in the high-density region is etched.
The first and second nitride films may be formed by a chemical vapor deposition process.
Alternatively, the first nitride film may be formed by a chemical vapor deposition process, and the second nitride film may be formed by a rapid thermal nitriding process. In this case, because the first nitride film can be formed to a desired thickness by the chemical vapor deposition process, the first nitride film can be formed to a thickness large enough to serve as an etching stopper for self-alignment. According to the rapid thermal nitriding process, inasmuch as a nitride film cannot be formed on the surfaces of the oxide films, after the oxide films on the surface of the semiconductor substrates on which the second nitride film is to be formed are removed, the exposed surface of the semiconductor substrate is heated in an ammonia atmosphere at a high temperature for a predetermined time to form the second nitride film. The rapid thermal nitriding process can form a nitride film of good quality though the formed nitride film is thinner than a nitride film formed by the chemical vapor deposition process, the rapid thermal nitriding process can be used to form the second nitride film which prevents an impurity of the interlayer insulating film from being diffused into the semiconductor substrate by annealing the assembly in the atmosphere containing the water vapor and also prevents the semiconductor substrate from being oxidized by annealing the assembly in the atmosphere containing the water vapor, but allows the forming gas to be diffused into the semiconductor substrate.
Preferably, the first nitride film should be formed to a thickness large enough to serve as an etching stopper for self-aligning the high-density region, and the second nitride film should be formed to a thickness which prevents an impurity of the interlayer insulating film from being diffused into the semiconductor substrate by annealing the assembly in the atmosphere containing the water vapor and also prevents the semiconductor substrate from being oxidized by annealing the assembly in the atmosphere containing the water vapor, but allows the forming gas to be diffused into the semiconductor substrate.
With the first and second nitride films having respective appropriated thicknesses, contact holes reaching the semiconductor substrate are formed in the interlayer insulating film by self-alignment in the high-density region.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.